<\/h1>\n\t\t\t\t<\/div>\n\t\t\t\t\n\t\t\t<\/div>\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\tProponer la selecci\u00f3n de ciertos equipos (arquitecturas computacionales) seg\u00fan los requerimientos de funcionalidad, rendimiento y costo, en laboratorios.<\/em><\/h5><\/div>\n\t\t\t<\/div>\n\t\t\t<\/div>\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t<\/div>\n\t\t\t\t\n\t\t\t\t\n\t\t\t<\/div>\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\tRealizaci\u00f3n de un procesador<\/h1><\/div>\n\t\t\t<\/div>\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\nDividimos nuestras microarquitecturas en dos partes interactivas: la ruta de datos y la unidad de control. La ruta de datos opera en palabras de datos. Contiene estructuras como memorias, registros, ALU y multiplexores. Estamos implementando la arquitectura ARM de 32 bits, por lo que usamos una ruta de datos de 32 bits.<\/p>\n
La unidad de control recibe la instrucci\u00f3n actual de la ruta de datos y le dice a la ruta de datos c\u00f3mo ejecutar esa instrucci\u00f3n. Espec\u00edficamente, la unidad de control produce se\u00f1ales de selecci\u00f3n de multiplexor, habilitaci\u00f3n de registro y escritura de memoria para controlar el funcionamiento de la ruta de datos.<\/p><\/div>\n\t\t\t<\/div>
\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t![\"Procesador](\"http:\/\/portafoliosfit.um.edu.mx\/sarahhdz\/wp-content\/uploads\/sites\/16\/2019\/05\/WhatsApp-Image-2019-05-06-at-2.15.46-PM.jpeg\" "\\"\\"")
<\/span><\/a>\n\t\t\t<\/div>\n\t\t\t<\/div>\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t<\/div>\n\t\t\t\t\n\t\t\t\t\n\t\t\t<\/div>\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\t- ARM<\/a><\/li>
- Controlador<\/a><\/li>
- Data path<\/a><\/li>
- Reg file<\/a><\/li>
- Extension<\/a><\/li>\n\t\t\t\t<\/ul>\n\t\t\t\t\n\t\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t
ARM - processor<\/h2>\n
Descripci\u00f3n:<\/strong> Nuestra \u00fanica entrada es la instrucci\u00f3n ya que la funci\u00f3n del procesador es procesar instrucciones.<\/p>\n\n- PC:<\/strong> devuelve el n\u00famero de la siguiente instrucci\u00f3n a ejecutar<\/li>\n
- Instr:<\/strong> contiene la instrucci\u00f3n a ejecutar<\/li>\n
- MemWrite:<\/strong> determina si se va a escribir en la memoria<\/li>\n
- ALUResult:<\/strong> WriteData: devuelve el resultado del ALU y el Data a escribir en la memoria<\/li>\n
- ReadData:<\/strong> es una entrada que muestra un dato de la memoria si la instrucci\u00f3n lo requiere<\/li>\n<\/ul>\n
![\"\"](\"http:\/\/portafoliosfit.um.edu.mx\/sarahhdz\/wp-content\/uploads\/sites\/16\/2019\/05\/ARm.png\")
<\/p><\/div>\n\t\t\t<\/div>
\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\tControlador<\/h2>\n
Descripci\u00f3n:<\/strong> El controlador es el que controla precisamente al datapath. Decodifica la instrucci\u00f3n para habilitar los componentes del datapath y utiliza un conditional check para verificar las condiciones de la instrucci\u00f3n, as\u00ed como la lectura y escritura de datos en la memoria.<\/p>\n\n- Instr: contiene la instrucci\u00f3n a decodificar<\/li>\n
- ALUFlags: contiene las flags que devuelve el ALU<\/li>\n
- RegSrc: Devuelve el registro origen<\/li>\n
- RegWrite: habilita la escritura en los registros del regFile<\/li>\n
- ImmSrc: Determina el tipo de operaci\u00f3n (procesamiento de datos, memoria o branches)<\/li>\n
- ALUSrc: Habilita la entrada de datos al ALU<\/li>\n
- ALUControl: Determina el tipo de operaci\u00f3n a realizar del ALU<\/li>\n
- MemWrite: Habilita la escritura en la memoria<\/li>\n
- MemtoReg: Permite escribir en un registro lo que hay en la memoria<\/li>\n
- PCSrc: Devuelve el PC del conditionalcheck<\/li>\n<\/ul>\n
![\"\"](\"http:\/\/portafoliosfit.um.edu.mx\/sarahhdz\/wp-content\/uploads\/sites\/16\/2019\/05\/controller.png\")
<\/p><\/div>\n\t\t\t<\/div>
\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\tDatapath<\/h2>\n
Descripci\u00f3n: <\/strong>determina el camino que los datos van a tomar y manda habilita los componentes seg\u00fan las se\u00f1ales del controlador.<\/p>\n\n- RegSrc: determina el tipo de operaci\u00f3n para el regFile<\/li>\n
- RegWrite: habilita escribir en los registros<\/li>\n
- ImmSrc: determina el tipo de operaci\u00f3n para la extensi\u00f3n (proceso de datos, memoria, branches)<\/li>\n
- ALUSrc: coloca inmediato o no<\/li>\n
- ALUControl: tipo de operaci\u00f3n del ALU<\/li>\n
- MemtoReg: si se escribe lo de la memoria en el resultado<\/li>\n
- PCSrc: dice cual ser\u00e1 la siguiente instrucci\u00f3n<\/li>\n
- ReadData: es la salid del data memory<\/li>\n
- PC: Es el n\u00famero de instrucci\u00f3n<\/li>\n
- Instr: la instrucci\u00f3n PC<\/li>\n
- ALUResult, WriteData: resultado del ALU, writeData es lo que se escribir\u00e1 en la memoria<\/li>\n
- ALUFlags: salida de las banderas del ALU<\/li>\n<\/ul>\n
![\"\"](\"http:\/\/portafoliosfit.um.edu.mx\/sarahhdz\/wp-content\/uploads\/sites\/16\/2019\/05\/datapath.png\")
<\/p><\/div>\n\t\t\t<\/div>
\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\tArchivo de registro<\/h2>\n
Descripci\u00f3n:\u00a0<\/strong>El circuito de registro consiste en multiples entradas tales como las entradas de registro de intrsucciones que tienen 4 bits, entradas de registro de 32 bits, un clk para la activaci\u00f3n de dicho componente, el cual se puene inicializar en cero o uno, y dos salidas de registros de 32 bits.<\/p>\n![\"\"](\"http:\/\/portafoliosfit.um.edu.mx\/sarahhdz\/wp-content\/uploads\/sites\/16\/2019\/05\/reg-file.png\")
![\"\"](\"http:\/\/portafoliosfit.um.edu.mx\/sarahhdz\/wp-content\/uploads\/sites\/16\/2019\/05\/reg-file-2.png\")
<\/p>\n
Habilitamos la escritura y escribimos un \u201c7\u201d en el Registro 15 como se muestra a continuaci\u00f3n. We3 habilita la escritura, wa3 es el registro destino y wd3 es la data a escribir.<\/p><\/div>\n\t\t\t<\/div>
\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\tExtensi\u00f3n<\/h2>\n
Descripci\u00f3n:\u00a0<\/strong>El circuito de extensi\u00f3n consiste en dos entradas, la instrucci\u00f3n de 24 bits e Inmediato de Origen de 2 bits (00,01,10) y una salida llamada extensi\u00f3n final de 32 bits.<\/p>\n![\"\"](\"http:\/\/portafoliosfit.um.edu.mx\/sarahhdz\/wp-content\/uploads\/sites\/16\/2019\/05\/extension.png\")
<\/p>\n
Tenemos en el immSrc un \u201c00\u201d que nos indica una operaci\u00f3n de procesamiento de datos. La instrucci\u00f3n del bit 0 al 23 nos indica que el inmediato es un 5. Por lo tanto la extensi\u00f3n nos devuelve un la instrucci\u00f3n del bit 0 al 7 con 24 \u201c0\u201d concatenados.<\/p><\/div>\n\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t<\/div>\n\t\t\t<\/div>\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t<\/div>\n\t\t\t\t\n\t\t\t\t\n\t\t\t<\/div>
\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\tC\u00f3digos<\/h1><\/div>\n\t\t\t<\/div>\n\t\t\t<\/div>\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t<\/div>\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\tARM<\/h5>\n\t\t\t\t\n <\/p>\n
library IEEE;\r\nuse IEEE.STD_LOGIC_1164.ALL;\r\nentity arm is\r\n-- Port ( );\r\n port(clk, reset: in STD_LOGIC;\r\n PC: out STD_LOGIC_VECTOR(31 downto 0);\r\n Instr: in STD_LOGIC_VECTOR(31 downto 0);\r\n MemWrite: out STD_LOGIC;\r\n ALUResult, WriteData: out STD_LOGIC_VECTOR(31 downto 0);\r\n ReadData: in STD_LOGIC_VECTOR(31 downto 0));\r\nend arm;\r\narchitecture struct of arm is\r\n component controller\r\n port(clk, reset: in STD_LOGIC;\r\n Instr: in STD_LOGIC_VECTOR(31 downto 12);\r\n ALUFlags: in STD_LOGIC_VECTOR(3 downto 0);\r\n RegSrc: out STD_LOGIC_VECTOR(1 downto 0);\r\n RegWrite: out STD_LOGIC;\r\n ImmSrc: out STD_LOGIC_VECTOR(1 downto 0);\r\n ALUSrc: out STD_LOGIC;\r\n ALUControl: out STD_LOGIC_VECTOR(1 downto 0);\r\n MemWrite: out STD_LOGIC;\r\n MemtoReg: out STD_LOGIC;\r\n PCSrc: out STD_LOGIC);\r\n end component;\r\n component datap\r\n port(clk, reset: in STD_LOGIC;\r\n RegSrc: in STD_LOGIC_VECTOR(1 downto 0);\r\n RegWrite: in STD_LOGIC;\r\n ImmSrc: in STD_LOGIC_VECTOR(1 downto 0);\r\n ALUSrc: in STD_LOGIC;\r\n ALUControl: in STD_LOGIC_VECTOR(1 downto 0);\r\n MemtoReg: in STD_LOGIC;\r\n PCSrc: in STD_LOGIC;\r\n ALUFlags: out STD_LOGIC_VECTOR(3 downto 0);\r\n PC: buffer STD_LOGIC_VECTOR(31 downto 0);\r\n Instr: in STD_LOGIC_VECTOR(31 downto 0);\r\n ALUResult, WriteData: buffer STD_LOGIC_VECTOR(31 downto 0);\r\n ReadData: in STD_LOGIC_VECTOR(31 downto 0));\r\n end component;\r\nsignal RegWrites, ALUSrcs, MemtoRegs, PCSrcs: STD_LOGIC;\r\nsignal RegSrcs, ImmSrcs, ALUControls: STD_LOGIC_VECTOR (1 downto 0);\r\nsignal ALUFlags: STD_LOGIC_VECTOR(3 downto 0);\r\nsignal PCs, ALUResults, WriteDatas: STD_LOGIC_VECTOR(31 downto 0);\r\nbegin\r\ncont: controller port map(clk, reset, Instr(31 downto 12), ALUFlags, RegSrcs, RegWrites, ImmSrcs, ALUSrcs, ALUControls, MemWrite, MemtoRegs, PCSrcs);\r\ndp: datap port map(clk, reset, RegSrcs, RegWrites, ImmSrcs, ALUSrcs, ALUControls, MemtoRegs, PCSrcs, ALUFlags, PCs, Instr, ALUResults, WriteDatas, ReadData);\r\n--RegWrite<=RegWritesgnl;\r\nALUResult<=ALUResults;\r\n--ReadData<=MemWritesgnl;\r\n--PCSrc<=PCSrcsgnl;\r\nPC<=PCs;\r\nWriteData<=WriteDatas;\r\nend;<\/pre><\/div>\n\t\t\t<\/div>\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\tController<\/h5>\n\t\t\t\t\n <\/p>\n
library IEEE;\r\nuse IEEE.STD_LOGIC_1164.ALL;\r\nentity controller is\r\n-- Port ( );\r\n port(clk, reset: in STD_LOGIC;\r\n Instr: in STD_LOGIC_VECTOR(31 downto 12);\r\n ALUFlags: in STD_LOGIC_VECTOR(3 downto 0);\r\n RegSrc: out STD_LOGIC_VECTOR(1 downto 0);\r\n RegWrite: out STD_LOGIC;\r\n ImmSrc: out STD_LOGIC_VECTOR(1 downto 0);\r\n ALUSrc: out STD_LOGIC;\r\n ALUControl: out STD_LOGIC_VECTOR(1 downto 0);\r\n MemWrite: out STD_LOGIC;\r\n MemtoReg: out STD_LOGIC;\r\n PCSrc: out STD_LOGIC);\r\nend controller;\r\narchitecture struct of controller is\r\n component decoder\r\n port(Op: in STD_LOGIC_VECTOR(1 downto 0);\r\n Funct: in STD_LOGIC_VECTOR(5 downto 0);\r\n Rd: in STD_LOGIC_VECTOR(3 downto 0);\r\n FlagW: out STD_LOGIC_VECTOR(1 downto 0);\r\n PCS, RegW, MemW: out STD_LOGIC;\r\n MemtoReg, ALUSrc: out STD_LOGIC;\r\n ImmSrc, RegSrc: out STD_LOGIC_VECTOR(1 downto 0);\r\n ALUControl: out STD_LOGIC_VECTOR(1 downto 0));\r\n end component;\r\n component conditional\r\n port(clk, reset: in STD_LOGIC;\r\n Cond: in STD_LOGIC_VECTOR(3 downto 0);\r\n ALUFlags: in STD_LOGIC_VECTOR(3 downto 0);\r\n FlagW: in STD_LOGIC_VECTOR(1 downto 0);\r\n PCS, RegW, MemW: in STD_LOGIC;\r\n PCSrc, RegWrite: out STD_LOGIC;\r\n MemWrite: out STD_LOGIC);\r\n end component;\r\nsignal FlagWsgnl: STD_LOGIC_VECTOR(1 downto 0);\r\nsignal PCSsgnl, RegWsgnl, MemWsgnl: STD_LOGIC;\r\nbegin\r\ndec: entity work.decoder port map(Op=>Instr(27 downto 26), Funct=>Instr(25 downto 20), Rd=>Instr(15 downto 12), FlagW=>FlagWsgnl, PCS=>PCSsgnl, RegW=>RegWsgnl, MemW=>MemWsgnl, MemtoReg=>MemtoReg, ALUSrc=>ALUSrc, ImmSrc=>ImmSrc, RegSrc=>RegSrc, ALUControl=>ALUControl);\r\ncl: entity work.conditional port map(clk=>clk, reset=>reset, Cond=>Instr(31 downto 28), ALUFlags=>ALUFlags, FlagW=>FlagWsgnl, PCS=>PCSsgnl, RegW=>RegWsgnl, MemW=>MemWsgnl, PCSrc=>PCSrc, RegWrite=>RegWrite, MemWrite=>MemWrite);\r\nend;<\/pre><\/div>\n\t\t\t<\/div>\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\tDatapath<\/h5>\n\t\t\t\t\n <\/p>\n
library IEEE;\r\nuse IEEE.STD_LOGIC_1164.ALL;\r\nentity datap is\r\n-- Port ( );\r\nport(clk, reset: in STD_LOGIC;\r\nRegSrc: in STD_LOGIC_VECTOR(1 downto 0);\r\nRegWrite: in STD_LOGIC;\r\nImmSrc: in STD_LOGIC_VECTOR(1 downto 0);\r\nALUSrc: in STD_LOGIC;\r\nALUControl: in STD_LOGIC_VECTOR(1 downto 0);\r\nMemtoReg: in STD_LOGIC;\r\nPCSrc: in STD_LOGIC;\r\nALUFlags: out STD_LOGIC_VECTOR(3 downto 0);\r\nPC: buffer STD_LOGIC_VECTOR(31 downto 0);\r\nInstr: in STD_LOGIC_VECTOR(31 downto 0);\r\nALUResult, WriteData: buffer STD_LOGIC_VECTOR(31 downto 0);\r\nReadData: in STD_LOGIC_VECTOR(31 downto 0));\r\nend datap;\r\narchitecture struct of datap is\r\ncomponent alu\r\ngeneric(M: integer :=32);\r\nPort (a,b : in STD_LOGIC_VECTOR (M-1 downto 0);\r\ncontrol : in STD_LOGIC_VECTOR (1 downto 0);\r\nresult : out STD_LOGIC_VECTOR (M-1 downto 0);\r\nflags : out STD_LOGIC_VECTOR (3 downto 0));\r\nend component;\r\ncomponent regfile\r\nport(clk: in STD_LOGIC;\r\nwe3: in STD_LOGIC;\r\nra1, ra2, wa3: in STD_LOGIC_VECTOR(3 downto 0);\r\nwd3, r15: in STD_LOGIC_VECTOR(31 downto 0);\r\nrd1, rd2: out STD_LOGIC_VECTOR(31 downto 0));\r\nend component;\r\ncomponent adder is\r\ngeneric(N: integer := 32);\r\nport(a, b: in STD_LOGIC_VECTOR(N-1 downto 0);\r\ns: out STD_LOGIC_VECTOR(N-1 downto 0);\r\ncin: in STD_LOGIC;\r\ncout: out STD_LOGIC);\r\nend component;\r\ncomponent immediate\r\nport(Instr: in STD_LOGIC_VECTOR(23 downto 0);\r\nImmSrc: in STD_LOGIC_VECTOR(1 downto 0);\r\nExtImm: out STD_LOGIC_VECTOR(31 downto 0));\r\nend component;\r\ncomponent flopenr generic(width: integer:= 4);\r\nport(clk, reset, en: in STD_LOGIC;\r\nd: in STD_LOGIC_VECTOR(width-1 downto 0);\r\nq: out STD_LOGIC_VECTOR(width-1 downto 0));\r\nend component;\r\ncomponent mux21 generic (N: integer:= 4);\r\nPort (c1, c2 : in STD_LOGIC_VECTOR (N-1 downto 0);\r\ns : in STD_LOGIC;\r\nz : out STD_LOGIC_VECTOR (N-1 downto 0));\r\nend component;\r\nsignal PCNext, PCPlus4, PCPlus8: STD_LOGIC_VECTOR(31 downto 0);\r\nsignal ExtImm, Result: STD_LOGIC_VECTOR(31 downto 0);\r\nsignal SrcA, SrcB: STD_LOGIC_VECTOR(31 downto 0);\r\nsignal RA1, RA2: STD_LOGIC_VECTOR(3 downto 0);\r\nsignal PCs: STD_LOGIC_VECTOR(31 downto 0);\r\nsignal writedatas: STD_LOGIC_VECTOR(31 downto 0);\r\nsignal aluresults: STD_LOGIC_VECTOR(31 downto 0);\r\nbegin\r\n-- next PC logic\r\npcmux: mux21 generic map(32) port map(PCPlus4, Result, PCSrc, PCNext);\r\npcreg: flopenr generic map(32) port map(clk, reset, '1', PCNext, pcs);\r\nPC<=pcs;\r\npcadd1: adder port map(PCs, X\"00000004\", PCPlus4,'0');\r\npcadd2: adder port map(PCPlus4, X\"00000004\", PCPlus8,'0');\r\n-- register file logic\r\nra1mux: mux21 generic map (4) port map(Instr(19 downto 16), \"1111\", RegSrc(0), RA1);\r\nra2mux: mux21 generic map (4) port map(Instr(3 downto 0), Instr(15 downto 12), RegSrc(1), RA2);\r\nrf: regfile port map(clk, RegWrite, RA1, RA2, Instr(15 downto 12), Result, PCPlus8, SrcA, writedatas);\r\nWriteData<=writedatas;\r\nresmux: mux21 generic map(32) port map(ALUResults, ReadData, MemtoReg, Result);\r\next: immediate port map(Instr(23 downto 0), ImmSrc, ExtImm);\r\n-- ALU logic\r\nsrcbmux: mux21 generic map(32) port map(writedatas, ExtImm, ALUSrc, SrcB);\r\ni_alu: alu port map(SrcA, SrcB, ALUControl, ALUResults, ALUFlags);\r\nALUResult<=ALUResults;\r\nend;<\/pre>\n <\/p>\n
<\/p><\/div>\n\t\t\t<\/div>\n\t\t\t<\/div>
\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\tRegfile<\/h5>\n\t\t\t\t\n <\/p>\n
library IEEE;\r\nuse IEEE.STD_LOGIC_1164.ALL;\r\nuse IEEE.STD_LOGIC_UNSIGNED.ALL;\r\nuse IEEE.NUMERIC_STD.ALL;\r\n\r\nentity regfile is -- three-port register file\r\n port(clk: in STD_LOGIC;\r\n we3: in STD_LOGIC;\r\n ra1, ra2, wa3: in STD_LOGIC_VECTOR(3 downto 0);\r\n wd3, r15: in STD_LOGIC_VECTOR(31 downto 0);\r\n rd1, rd2: out STD_LOGIC_VECTOR(31 downto 0));\r\nend;\r\n\r\narchitecture behave of regfile is\r\n type ramtype is array (31 downto 0) of\r\n STD_LOGIC_VECTOR(31 downto 0);\r\n signal mem: ramtype;\r\n \r\nbegin\r\n process(clk) begin\r\n if rising_edge(clk) then\r\n if we3 = '1' then \r\n mem(to_integer(unsigned(wa3))) <= wd3;\r\n end if;\r\n end if;\r\n end process;\r\n process(clk, we3, ra1, ra2, wa3, wd3, r15) begin\r\n if (to_integer(unsigned(ra1)) = 15) then \r\n rd1 <= r15;\r\n else \r\n rd1 <= mem(to_integer(unsigned(ra1)));\r\n end if;\r\n if (to_integer(unsigned(ra2)) = 15) then \r\n rd2 <= r15;\r\n else \r\n rd2 <= mem(to_integer(unsigned(ra2)));\r\n end if;\r\n end process;\r\nend;<\/pre>\n <\/p>\n
<\/p><\/div>\n\t\t\t<\/div>
\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\tExtension<\/h5>\n\t\t\t\t\n <\/p>\n
library IEEE; \r\nuse IEEE.STD_LOGIC_1164.all;\r\nentity extend is\r\n port(Instr: in STD_LOGIC_VECTOR(23 downto 0);\r\n ImmSrc: in STD_LOGIC_VECTOR(1 downto 0);\r\n ExtImm: out STD_LOGIC_VECTOR(31 downto 0));\r\nend;\r\narchitecture behave of extend is\r\nbegin\r\n process(Instr, ImmSrc) \r\n begin\r\n case ImmSrc is\r\n when \"00\" => \r\n ExtImm <= (X\"000000\"&Instr(7 downto 0));\r\n when \"01\" => \r\n ExtImm <= (X\"00000\"&Instr(11 downto 0));\r\n when \"10\" => ExtImm <= (Instr(23) & Instr(23) & Instr(23)&Instr(23) & \r\n Instr(23)&Instr(23) & Instr(23 downto 0) & \"00\");\r\n when others => ExtImm <= (others => '-');\r\n end case;\r\n end process;\r\nend;<\/pre>\n <\/p>\n
<\/p><\/div>\n\t\t\t<\/div>\n\t\t\t<\/div>\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t<\/div>\n\t\t\t\t\n\t\t\t\t\n\t\t\t<\/div>
\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\u00a0<\/p>\n
Reflexi\u00f3n<\/h3>\n
El n\u00famero de instrucciones en un programa depende de la arquitectura del procesador. Algunas arquitecturas tienen instrucciones complicadas que hacen m\u00e1s trabajo por instrucci\u00f3n, lo que reduce el n\u00famero de instrucciones en un programa. Sin embargo, estas instrucciones complicadas suelen ser m\u00e1s lentas de ejecutar en hardware.<\/p>\n
La computadora maneja un lenguaje binario. A trav\u00e9s del lenguaje ensamblador, los lenguajes de programaci\u00f3n, diversas interfaces, compiladores y dem\u00e1s podemos facilitar la interacci\u00f3n hombre-m\u00e1quina.<\/p>\n
\u00a0<\/p><\/div>\n\t\t\t<\/div>\n\t\t\t<\/div>\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t<\/div>\n\t\t\t\t\n\t\t\t\t\n\t\t\t<\/div><\/p>\n","protected":false},"excerpt":{"rendered":"","protected":false},"author":18,"featured_media":902,"comment_status":"open","ping_status":"closed","template":"","meta":{"_et_pb_use_builder":"on","_et_pb_old_content":"","_et_gb_content_width":"","footnotes":""},"project_category":[16],"project_tag":[],"class_list":["post-752","project","type-project","status-publish","has-post-thumbnail","hentry","project_category-portafolio-ii"],"_links":{"self":[{"href":"https:\/\/portafoliosfit.um.edu.mx\/sarahhdz\/wp-json\/wp\/v2\/project\/752","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/portafoliosfit.um.edu.mx\/sarahhdz\/wp-json\/wp\/v2\/project"}],"about":[{"href":"https:\/\/portafoliosfit.um.edu.mx\/sarahhdz\/wp-json\/wp\/v2\/types\/project"}],"author":[{"embeddable":true,"href":"https:\/\/portafoliosfit.um.edu.mx\/sarahhdz\/wp-json\/wp\/v2\/users\/18"}],"replies":[{"embeddable":true,"href":"https:\/\/portafoliosfit.um.edu.mx\/sarahhdz\/wp-json\/wp\/v2\/comments?post=752"}],"version-history":[{"count":63,"href":"https:\/\/portafoliosfit.um.edu.mx\/sarahhdz\/wp-json\/wp\/v2\/project\/752\/revisions"}],"predecessor-version":[{"id":1054,"href":"https:\/\/portafoliosfit.um.edu.mx\/sarahhdz\/wp-json\/wp\/v2\/project\/752\/revisions\/1054"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/portafoliosfit.um.edu.mx\/sarahhdz\/wp-json\/wp\/v2\/media\/902"}],"wp:attachment":[{"href":"https:\/\/portafoliosfit.um.edu.mx\/sarahhdz\/wp-json\/wp\/v2\/media?parent=752"}],"wp:term":[{"taxonomy":"project_category","embeddable":true,"href":"https:\/\/portafoliosfit.um.edu.mx\/sarahhdz\/wp-json\/wp\/v2\/project_category?post=752"},{"taxonomy":"project_tag","embeddable":true,"href":"https:\/\/portafoliosfit.um.edu.mx\/sarahhdz\/wp-json\/wp\/v2\/project_tag?post=752"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}
Proponer la selecci\u00f3n de ciertos equipos (arquitecturas computacionales) seg\u00fan los requerimientos de funcionalidad, rendimiento y costo, en laboratorios.<\/em><\/h5><\/div>\n\t\t\t<\/div>\n\t\t\t<\/div>\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t<\/div>\n\t\t\t\t\n\t\t\t\t\n\t\t\t<\/div>\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\tRealizaci\u00f3n de un procesador<\/h1><\/div>\n\t\t\t<\/div>\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\nDividimos nuestras microarquitecturas en dos partes interactivas: la ruta de datos y la unidad de control. La ruta de datos opera en palabras de datos. Contiene estructuras como memorias, registros, ALU y multiplexores. Estamos implementando la arquitectura ARM de 32 bits, por lo que usamos una ruta de datos de 32 bits.<\/p>\n
La unidad de control recibe la instrucci\u00f3n actual de la ruta de datos y le dice a la ruta de datos c\u00f3mo ejecutar esa instrucci\u00f3n. Espec\u00edficamente, la unidad de control produce se\u00f1ales de selecci\u00f3n de multiplexor, habilitaci\u00f3n de registro y escritura de memoria para controlar el funcionamiento de la ruta de datos.<\/p><\/div>\n\t\t\t<\/div>
\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t<\/span><\/a>\n\t\t\t<\/div>\n\t\t\t<\/div>\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t<\/div>\n\t\t\t\t\n\t\t\t\t\n\t\t\t<\/div>\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\t- ARM<\/a><\/li>
- Controlador<\/a><\/li>
- Data path<\/a><\/li>
- Reg file<\/a><\/li>
- Extension<\/a><\/li>\n\t\t\t\t<\/ul>\n\t\t\t\t\n\t\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t
ARM - processor<\/h2>\n
Descripci\u00f3n:<\/strong> Nuestra \u00fanica entrada es la instrucci\u00f3n ya que la funci\u00f3n del procesador es procesar instrucciones.<\/p>\n\n- PC:<\/strong> devuelve el n\u00famero de la siguiente instrucci\u00f3n a ejecutar<\/li>\n
- Instr:<\/strong> contiene la instrucci\u00f3n a ejecutar<\/li>\n
- MemWrite:<\/strong> determina si se va a escribir en la memoria<\/li>\n
- ALUResult:<\/strong> WriteData: devuelve el resultado del ALU y el Data a escribir en la memoria<\/li>\n
- ReadData:<\/strong> es una entrada que muestra un dato de la memoria si la instrucci\u00f3n lo requiere<\/li>\n<\/ul>\n
<\/p><\/div>\n\t\t\t<\/div>
\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\tControlador<\/h2>\n
Descripci\u00f3n:<\/strong> El controlador es el que controla precisamente al datapath. Decodifica la instrucci\u00f3n para habilitar los componentes del datapath y utiliza un conditional check para verificar las condiciones de la instrucci\u00f3n, as\u00ed como la lectura y escritura de datos en la memoria.<\/p>\n\n- Instr: contiene la instrucci\u00f3n a decodificar<\/li>\n
- ALUFlags: contiene las flags que devuelve el ALU<\/li>\n
- RegSrc: Devuelve el registro origen<\/li>\n
- RegWrite: habilita la escritura en los registros del regFile<\/li>\n
- ImmSrc: Determina el tipo de operaci\u00f3n (procesamiento de datos, memoria o branches)<\/li>\n
- ALUSrc: Habilita la entrada de datos al ALU<\/li>\n
- ALUControl: Determina el tipo de operaci\u00f3n a realizar del ALU<\/li>\n
- MemWrite: Habilita la escritura en la memoria<\/li>\n
- MemtoReg: Permite escribir en un registro lo que hay en la memoria<\/li>\n
- PCSrc: Devuelve el PC del conditionalcheck<\/li>\n<\/ul>\n
<\/p><\/div>\n\t\t\t<\/div>
\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\tDatapath<\/h2>\n
Descripci\u00f3n: <\/strong>determina el camino que los datos van a tomar y manda habilita los componentes seg\u00fan las se\u00f1ales del controlador.<\/p>\n\n- RegSrc: determina el tipo de operaci\u00f3n para el regFile<\/li>\n
- RegWrite: habilita escribir en los registros<\/li>\n
- ImmSrc: determina el tipo de operaci\u00f3n para la extensi\u00f3n (proceso de datos, memoria, branches)<\/li>\n
- ALUSrc: coloca inmediato o no<\/li>\n
- ALUControl: tipo de operaci\u00f3n del ALU<\/li>\n
- MemtoReg: si se escribe lo de la memoria en el resultado<\/li>\n
- PCSrc: dice cual ser\u00e1 la siguiente instrucci\u00f3n<\/li>\n
- ReadData: es la salid del data memory<\/li>\n
- PC: Es el n\u00famero de instrucci\u00f3n<\/li>\n
- Instr: la instrucci\u00f3n PC<\/li>\n
- ALUResult, WriteData: resultado del ALU, writeData es lo que se escribir\u00e1 en la memoria<\/li>\n
- ALUFlags: salida de las banderas del ALU<\/li>\n<\/ul>\n
<\/p><\/div>\n\t\t\t<\/div>
\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\tArchivo de registro<\/h2>\n
Descripci\u00f3n:\u00a0<\/strong>El circuito de registro consiste en multiples entradas tales como las entradas de registro de intrsucciones que tienen 4 bits, entradas de registro de 32 bits, un clk para la activaci\u00f3n de dicho componente, el cual se puene inicializar en cero o uno, y dos salidas de registros de 32 bits.<\/p>\n<\/p>\n
Habilitamos la escritura y escribimos un \u201c7\u201d en el Registro 15 como se muestra a continuaci\u00f3n. We3 habilita la escritura, wa3 es el registro destino y wd3 es la data a escribir.<\/p><\/div>\n\t\t\t<\/div>
\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\tExtensi\u00f3n<\/h2>\n
Descripci\u00f3n:\u00a0<\/strong>El circuito de extensi\u00f3n consiste en dos entradas, la instrucci\u00f3n de 24 bits e Inmediato de Origen de 2 bits (00,01,10) y una salida llamada extensi\u00f3n final de 32 bits.<\/p>\n<\/p>\n
Tenemos en el immSrc un \u201c00\u201d que nos indica una operaci\u00f3n de procesamiento de datos. La instrucci\u00f3n del bit 0 al 23 nos indica que el inmediato es un 5. Por lo tanto la extensi\u00f3n nos devuelve un la instrucci\u00f3n del bit 0 al 7 con 24 \u201c0\u201d concatenados.<\/p><\/div>\n\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t<\/div>\n\t\t\t<\/div>\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t<\/div>\n\t\t\t\t\n\t\t\t\t\n\t\t\t<\/div>
\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\tC\u00f3digos<\/h1><\/div>\n\t\t\t<\/div>\n\t\t\t<\/div>\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t<\/div>\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\tARM<\/h5>\n\t\t\t\t\n <\/p>\n
library IEEE;\r\nuse IEEE.STD_LOGIC_1164.ALL;\r\nentity arm is\r\n-- Port ( );\r\n port(clk, reset: in STD_LOGIC;\r\n PC: out STD_LOGIC_VECTOR(31 downto 0);\r\n Instr: in STD_LOGIC_VECTOR(31 downto 0);\r\n MemWrite: out STD_LOGIC;\r\n ALUResult, WriteData: out STD_LOGIC_VECTOR(31 downto 0);\r\n ReadData: in STD_LOGIC_VECTOR(31 downto 0));\r\nend arm;\r\narchitecture struct of arm is\r\n component controller\r\n port(clk, reset: in STD_LOGIC;\r\n Instr: in STD_LOGIC_VECTOR(31 downto 12);\r\n ALUFlags: in STD_LOGIC_VECTOR(3 downto 0);\r\n RegSrc: out STD_LOGIC_VECTOR(1 downto 0);\r\n RegWrite: out STD_LOGIC;\r\n ImmSrc: out STD_LOGIC_VECTOR(1 downto 0);\r\n ALUSrc: out STD_LOGIC;\r\n ALUControl: out STD_LOGIC_VECTOR(1 downto 0);\r\n MemWrite: out STD_LOGIC;\r\n MemtoReg: out STD_LOGIC;\r\n PCSrc: out STD_LOGIC);\r\n end component;\r\n component datap\r\n port(clk, reset: in STD_LOGIC;\r\n RegSrc: in STD_LOGIC_VECTOR(1 downto 0);\r\n RegWrite: in STD_LOGIC;\r\n ImmSrc: in STD_LOGIC_VECTOR(1 downto 0);\r\n ALUSrc: in STD_LOGIC;\r\n ALUControl: in STD_LOGIC_VECTOR(1 downto 0);\r\n MemtoReg: in STD_LOGIC;\r\n PCSrc: in STD_LOGIC;\r\n ALUFlags: out STD_LOGIC_VECTOR(3 downto 0);\r\n PC: buffer STD_LOGIC_VECTOR(31 downto 0);\r\n Instr: in STD_LOGIC_VECTOR(31 downto 0);\r\n ALUResult, WriteData: buffer STD_LOGIC_VECTOR(31 downto 0);\r\n ReadData: in STD_LOGIC_VECTOR(31 downto 0));\r\n end component;\r\nsignal RegWrites, ALUSrcs, MemtoRegs, PCSrcs: STD_LOGIC;\r\nsignal RegSrcs, ImmSrcs, ALUControls: STD_LOGIC_VECTOR (1 downto 0);\r\nsignal ALUFlags: STD_LOGIC_VECTOR(3 downto 0);\r\nsignal PCs, ALUResults, WriteDatas: STD_LOGIC_VECTOR(31 downto 0);\r\nbegin\r\ncont: controller port map(clk, reset, Instr(31 downto 12), ALUFlags, RegSrcs, RegWrites, ImmSrcs, ALUSrcs, ALUControls, MemWrite, MemtoRegs, PCSrcs);\r\ndp: datap port map(clk, reset, RegSrcs, RegWrites, ImmSrcs, ALUSrcs, ALUControls, MemtoRegs, PCSrcs, ALUFlags, PCs, Instr, ALUResults, WriteDatas, ReadData);\r\n--RegWrite<=RegWritesgnl;\r\nALUResult<=ALUResults;\r\n--ReadData<=MemWritesgnl;\r\n--PCSrc<=PCSrcsgnl;\r\nPC<=PCs;\r\nWriteData<=WriteDatas;\r\nend;<\/pre><\/div>\n\t\t\t<\/div>\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\tController<\/h5>\n\t\t\t\t\n <\/p>\n
library IEEE;\r\nuse IEEE.STD_LOGIC_1164.ALL;\r\nentity controller is\r\n-- Port ( );\r\n port(clk, reset: in STD_LOGIC;\r\n Instr: in STD_LOGIC_VECTOR(31 downto 12);\r\n ALUFlags: in STD_LOGIC_VECTOR(3 downto 0);\r\n RegSrc: out STD_LOGIC_VECTOR(1 downto 0);\r\n RegWrite: out STD_LOGIC;\r\n ImmSrc: out STD_LOGIC_VECTOR(1 downto 0);\r\n ALUSrc: out STD_LOGIC;\r\n ALUControl: out STD_LOGIC_VECTOR(1 downto 0);\r\n MemWrite: out STD_LOGIC;\r\n MemtoReg: out STD_LOGIC;\r\n PCSrc: out STD_LOGIC);\r\nend controller;\r\narchitecture struct of controller is\r\n component decoder\r\n port(Op: in STD_LOGIC_VECTOR(1 downto 0);\r\n Funct: in STD_LOGIC_VECTOR(5 downto 0);\r\n Rd: in STD_LOGIC_VECTOR(3 downto 0);\r\n FlagW: out STD_LOGIC_VECTOR(1 downto 0);\r\n PCS, RegW, MemW: out STD_LOGIC;\r\n MemtoReg, ALUSrc: out STD_LOGIC;\r\n ImmSrc, RegSrc: out STD_LOGIC_VECTOR(1 downto 0);\r\n ALUControl: out STD_LOGIC_VECTOR(1 downto 0));\r\n end component;\r\n component conditional\r\n port(clk, reset: in STD_LOGIC;\r\n Cond: in STD_LOGIC_VECTOR(3 downto 0);\r\n ALUFlags: in STD_LOGIC_VECTOR(3 downto 0);\r\n FlagW: in STD_LOGIC_VECTOR(1 downto 0);\r\n PCS, RegW, MemW: in STD_LOGIC;\r\n PCSrc, RegWrite: out STD_LOGIC;\r\n MemWrite: out STD_LOGIC);\r\n end component;\r\nsignal FlagWsgnl: STD_LOGIC_VECTOR(1 downto 0);\r\nsignal PCSsgnl, RegWsgnl, MemWsgnl: STD_LOGIC;\r\nbegin\r\ndec: entity work.decoder port map(Op=>Instr(27 downto 26), Funct=>Instr(25 downto 20), Rd=>Instr(15 downto 12), FlagW=>FlagWsgnl, PCS=>PCSsgnl, RegW=>RegWsgnl, MemW=>MemWsgnl, MemtoReg=>MemtoReg, ALUSrc=>ALUSrc, ImmSrc=>ImmSrc, RegSrc=>RegSrc, ALUControl=>ALUControl);\r\ncl: entity work.conditional port map(clk=>clk, reset=>reset, Cond=>Instr(31 downto 28), ALUFlags=>ALUFlags, FlagW=>FlagWsgnl, PCS=>PCSsgnl, RegW=>RegWsgnl, MemW=>MemWsgnl, PCSrc=>PCSrc, RegWrite=>RegWrite, MemWrite=>MemWrite);\r\nend;<\/pre><\/div>\n\t\t\t<\/div>\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\tDatapath<\/h5>\n\t\t\t\t\n <\/p>\n
library IEEE;\r\nuse IEEE.STD_LOGIC_1164.ALL;\r\nentity datap is\r\n-- Port ( );\r\nport(clk, reset: in STD_LOGIC;\r\nRegSrc: in STD_LOGIC_VECTOR(1 downto 0);\r\nRegWrite: in STD_LOGIC;\r\nImmSrc: in STD_LOGIC_VECTOR(1 downto 0);\r\nALUSrc: in STD_LOGIC;\r\nALUControl: in STD_LOGIC_VECTOR(1 downto 0);\r\nMemtoReg: in STD_LOGIC;\r\nPCSrc: in STD_LOGIC;\r\nALUFlags: out STD_LOGIC_VECTOR(3 downto 0);\r\nPC: buffer STD_LOGIC_VECTOR(31 downto 0);\r\nInstr: in STD_LOGIC_VECTOR(31 downto 0);\r\nALUResult, WriteData: buffer STD_LOGIC_VECTOR(31 downto 0);\r\nReadData: in STD_LOGIC_VECTOR(31 downto 0));\r\nend datap;\r\narchitecture struct of datap is\r\ncomponent alu\r\ngeneric(M: integer :=32);\r\nPort (a,b : in STD_LOGIC_VECTOR (M-1 downto 0);\r\ncontrol : in STD_LOGIC_VECTOR (1 downto 0);\r\nresult : out STD_LOGIC_VECTOR (M-1 downto 0);\r\nflags : out STD_LOGIC_VECTOR (3 downto 0));\r\nend component;\r\ncomponent regfile\r\nport(clk: in STD_LOGIC;\r\nwe3: in STD_LOGIC;\r\nra1, ra2, wa3: in STD_LOGIC_VECTOR(3 downto 0);\r\nwd3, r15: in STD_LOGIC_VECTOR(31 downto 0);\r\nrd1, rd2: out STD_LOGIC_VECTOR(31 downto 0));\r\nend component;\r\ncomponent adder is\r\ngeneric(N: integer := 32);\r\nport(a, b: in STD_LOGIC_VECTOR(N-1 downto 0);\r\ns: out STD_LOGIC_VECTOR(N-1 downto 0);\r\ncin: in STD_LOGIC;\r\ncout: out STD_LOGIC);\r\nend component;\r\ncomponent immediate\r\nport(Instr: in STD_LOGIC_VECTOR(23 downto 0);\r\nImmSrc: in STD_LOGIC_VECTOR(1 downto 0);\r\nExtImm: out STD_LOGIC_VECTOR(31 downto 0));\r\nend component;\r\ncomponent flopenr generic(width: integer:= 4);\r\nport(clk, reset, en: in STD_LOGIC;\r\nd: in STD_LOGIC_VECTOR(width-1 downto 0);\r\nq: out STD_LOGIC_VECTOR(width-1 downto 0));\r\nend component;\r\ncomponent mux21 generic (N: integer:= 4);\r\nPort (c1, c2 : in STD_LOGIC_VECTOR (N-1 downto 0);\r\ns : in STD_LOGIC;\r\nz : out STD_LOGIC_VECTOR (N-1 downto 0));\r\nend component;\r\nsignal PCNext, PCPlus4, PCPlus8: STD_LOGIC_VECTOR(31 downto 0);\r\nsignal ExtImm, Result: STD_LOGIC_VECTOR(31 downto 0);\r\nsignal SrcA, SrcB: STD_LOGIC_VECTOR(31 downto 0);\r\nsignal RA1, RA2: STD_LOGIC_VECTOR(3 downto 0);\r\nsignal PCs: STD_LOGIC_VECTOR(31 downto 0);\r\nsignal writedatas: STD_LOGIC_VECTOR(31 downto 0);\r\nsignal aluresults: STD_LOGIC_VECTOR(31 downto 0);\r\nbegin\r\n-- next PC logic\r\npcmux: mux21 generic map(32) port map(PCPlus4, Result, PCSrc, PCNext);\r\npcreg: flopenr generic map(32) port map(clk, reset, '1', PCNext, pcs);\r\nPC<=pcs;\r\npcadd1: adder port map(PCs, X\"00000004\", PCPlus4,'0');\r\npcadd2: adder port map(PCPlus4, X\"00000004\", PCPlus8,'0');\r\n-- register file logic\r\nra1mux: mux21 generic map (4) port map(Instr(19 downto 16), \"1111\", RegSrc(0), RA1);\r\nra2mux: mux21 generic map (4) port map(Instr(3 downto 0), Instr(15 downto 12), RegSrc(1), RA2);\r\nrf: regfile port map(clk, RegWrite, RA1, RA2, Instr(15 downto 12), Result, PCPlus8, SrcA, writedatas);\r\nWriteData<=writedatas;\r\nresmux: mux21 generic map(32) port map(ALUResults, ReadData, MemtoReg, Result);\r\next: immediate port map(Instr(23 downto 0), ImmSrc, ExtImm);\r\n-- ALU logic\r\nsrcbmux: mux21 generic map(32) port map(writedatas, ExtImm, ALUSrc, SrcB);\r\ni_alu: alu port map(SrcA, SrcB, ALUControl, ALUResults, ALUFlags);\r\nALUResult<=ALUResults;\r\nend;<\/pre>\n <\/p>\n
<\/p><\/div>\n\t\t\t<\/div>\n\t\t\t<\/div>
\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\tRegfile<\/h5>\n\t\t\t\t\n <\/p>\n
library IEEE;\r\nuse IEEE.STD_LOGIC_1164.ALL;\r\nuse IEEE.STD_LOGIC_UNSIGNED.ALL;\r\nuse IEEE.NUMERIC_STD.ALL;\r\n\r\nentity regfile is -- three-port register file\r\n port(clk: in STD_LOGIC;\r\n we3: in STD_LOGIC;\r\n ra1, ra2, wa3: in STD_LOGIC_VECTOR(3 downto 0);\r\n wd3, r15: in STD_LOGIC_VECTOR(31 downto 0);\r\n rd1, rd2: out STD_LOGIC_VECTOR(31 downto 0));\r\nend;\r\n\r\narchitecture behave of regfile is\r\n type ramtype is array (31 downto 0) of\r\n STD_LOGIC_VECTOR(31 downto 0);\r\n signal mem: ramtype;\r\n \r\nbegin\r\n process(clk) begin\r\n if rising_edge(clk) then\r\n if we3 = '1' then \r\n mem(to_integer(unsigned(wa3))) <= wd3;\r\n end if;\r\n end if;\r\n end process;\r\n process(clk, we3, ra1, ra2, wa3, wd3, r15) begin\r\n if (to_integer(unsigned(ra1)) = 15) then \r\n rd1 <= r15;\r\n else \r\n rd1 <= mem(to_integer(unsigned(ra1)));\r\n end if;\r\n if (to_integer(unsigned(ra2)) = 15) then \r\n rd2 <= r15;\r\n else \r\n rd2 <= mem(to_integer(unsigned(ra2)));\r\n end if;\r\n end process;\r\nend;<\/pre>\n <\/p>\n
<\/p><\/div>\n\t\t\t<\/div>
\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\tExtension<\/h5>\n\t\t\t\t\n <\/p>\n
library IEEE; \r\nuse IEEE.STD_LOGIC_1164.all;\r\nentity extend is\r\n port(Instr: in STD_LOGIC_VECTOR(23 downto 0);\r\n ImmSrc: in STD_LOGIC_VECTOR(1 downto 0);\r\n ExtImm: out STD_LOGIC_VECTOR(31 downto 0));\r\nend;\r\narchitecture behave of extend is\r\nbegin\r\n process(Instr, ImmSrc) \r\n begin\r\n case ImmSrc is\r\n when \"00\" => \r\n ExtImm <= (X\"000000\"&Instr(7 downto 0));\r\n when \"01\" => \r\n ExtImm <= (X\"00000\"&Instr(11 downto 0));\r\n when \"10\" => ExtImm <= (Instr(23) & Instr(23) & Instr(23)&Instr(23) & \r\n Instr(23)&Instr(23) & Instr(23 downto 0) & \"00\");\r\n when others => ExtImm <= (others => '-');\r\n end case;\r\n end process;\r\nend;<\/pre>\n <\/p>\n
<\/p><\/div>\n\t\t\t<\/div>\n\t\t\t<\/div>\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t<\/div>\n\t\t\t\t\n\t\t\t\t\n\t\t\t<\/div>
\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\u00a0<\/p>\n
Reflexi\u00f3n<\/h3>\n
El n\u00famero de instrucciones en un programa depende de la arquitectura del procesador. Algunas arquitecturas tienen instrucciones complicadas que hacen m\u00e1s trabajo por instrucci\u00f3n, lo que reduce el n\u00famero de instrucciones en un programa. Sin embargo, estas instrucciones complicadas suelen ser m\u00e1s lentas de ejecutar en hardware.<\/p>\n
La computadora maneja un lenguaje binario. A trav\u00e9s del lenguaje ensamblador, los lenguajes de programaci\u00f3n, diversas interfaces, compiladores y dem\u00e1s podemos facilitar la interacci\u00f3n hombre-m\u00e1quina.<\/p>\n
\u00a0<\/p><\/div>\n\t\t\t<\/div>\n\t\t\t<\/div>\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t<\/div>\n\t\t\t\t\n\t\t\t\t\n\t\t\t<\/div><\/p>\n","protected":false},"excerpt":{"rendered":"","protected":false},"author":18,"featured_media":902,"comment_status":"open","ping_status":"closed","template":"","meta":{"_et_pb_use_builder":"on","_et_pb_old_content":"","_et_gb_content_width":"","footnotes":""},"project_category":[16],"project_tag":[],"class_list":["post-752","project","type-project","status-publish","has-post-thumbnail","hentry","project_category-portafolio-ii"],"_links":{"self":[{"href":"https:\/\/portafoliosfit.um.edu.mx\/sarahhdz\/wp-json\/wp\/v2\/project\/752","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/portafoliosfit.um.edu.mx\/sarahhdz\/wp-json\/wp\/v2\/project"}],"about":[{"href":"https:\/\/portafoliosfit.um.edu.mx\/sarahhdz\/wp-json\/wp\/v2\/types\/project"}],"author":[{"embeddable":true,"href":"https:\/\/portafoliosfit.um.edu.mx\/sarahhdz\/wp-json\/wp\/v2\/users\/18"}],"replies":[{"embeddable":true,"href":"https:\/\/portafoliosfit.um.edu.mx\/sarahhdz\/wp-json\/wp\/v2\/comments?post=752"}],"version-history":[{"count":63,"href":"https:\/\/portafoliosfit.um.edu.mx\/sarahhdz\/wp-json\/wp\/v2\/project\/752\/revisions"}],"predecessor-version":[{"id":1054,"href":"https:\/\/portafoliosfit.um.edu.mx\/sarahhdz\/wp-json\/wp\/v2\/project\/752\/revisions\/1054"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/portafoliosfit.um.edu.mx\/sarahhdz\/wp-json\/wp\/v2\/media\/902"}],"wp:attachment":[{"href":"https:\/\/portafoliosfit.um.edu.mx\/sarahhdz\/wp-json\/wp\/v2\/media?parent=752"}],"wp:term":[{"taxonomy":"project_category","embeddable":true,"href":"https:\/\/portafoliosfit.um.edu.mx\/sarahhdz\/wp-json\/wp\/v2\/project_category?post=752"},{"taxonomy":"project_tag","embeddable":true,"href":"https:\/\/portafoliosfit.um.edu.mx\/sarahhdz\/wp-json\/wp\/v2\/project_tag?post=752"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}
Realizaci\u00f3n de un procesador<\/h1><\/div>\n\t\t\t<\/div>\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\nDividimos nuestras microarquitecturas en dos partes interactivas: la ruta de datos y la unidad de control. La ruta de datos opera en palabras de datos. Contiene estructuras como memorias, registros, ALU y multiplexores. Estamos implementando la arquitectura ARM de 32 bits, por lo que usamos una ruta de datos de 32 bits.<\/p>\n
La unidad de control recibe la instrucci\u00f3n actual de la ruta de datos y le dice a la ruta de datos c\u00f3mo ejecutar esa instrucci\u00f3n. Espec\u00edficamente, la unidad de control produce se\u00f1ales de selecci\u00f3n de multiplexor, habilitaci\u00f3n de registro y escritura de memoria para controlar el funcionamiento de la ruta de datos.<\/p><\/div>\n\t\t\t<\/div>
\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t<\/span><\/a>\n\t\t\t<\/div>\n\t\t\t<\/div>\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t<\/div>\n\t\t\t\t\n\t\t\t\t\n\t\t\t<\/div>\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\t- ARM<\/a><\/li>
- Controlador<\/a><\/li>
- Data path<\/a><\/li>
- Reg file<\/a><\/li>
- Extension<\/a><\/li>\n\t\t\t\t<\/ul>\n\t\t\t\t\n\t\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t
ARM - processor<\/h2>\n
Descripci\u00f3n:<\/strong> Nuestra \u00fanica entrada es la instrucci\u00f3n ya que la funci\u00f3n del procesador es procesar instrucciones.<\/p>\n\n- PC:<\/strong> devuelve el n\u00famero de la siguiente instrucci\u00f3n a ejecutar<\/li>\n
- Instr:<\/strong> contiene la instrucci\u00f3n a ejecutar<\/li>\n
- MemWrite:<\/strong> determina si se va a escribir en la memoria<\/li>\n
- ALUResult:<\/strong> WriteData: devuelve el resultado del ALU y el Data a escribir en la memoria<\/li>\n
- ReadData:<\/strong> es una entrada que muestra un dato de la memoria si la instrucci\u00f3n lo requiere<\/li>\n<\/ul>\n
<\/p><\/div>\n\t\t\t<\/div>
\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\tControlador<\/h2>\n
Descripci\u00f3n:<\/strong> El controlador es el que controla precisamente al datapath. Decodifica la instrucci\u00f3n para habilitar los componentes del datapath y utiliza un conditional check para verificar las condiciones de la instrucci\u00f3n, as\u00ed como la lectura y escritura de datos en la memoria.<\/p>\n\n- Instr: contiene la instrucci\u00f3n a decodificar<\/li>\n
- ALUFlags: contiene las flags que devuelve el ALU<\/li>\n
- RegSrc: Devuelve el registro origen<\/li>\n
- RegWrite: habilita la escritura en los registros del regFile<\/li>\n
- ImmSrc: Determina el tipo de operaci\u00f3n (procesamiento de datos, memoria o branches)<\/li>\n
- ALUSrc: Habilita la entrada de datos al ALU<\/li>\n
- ALUControl: Determina el tipo de operaci\u00f3n a realizar del ALU<\/li>\n
- MemWrite: Habilita la escritura en la memoria<\/li>\n
- MemtoReg: Permite escribir en un registro lo que hay en la memoria<\/li>\n
- PCSrc: Devuelve el PC del conditionalcheck<\/li>\n<\/ul>\n
<\/p><\/div>\n\t\t\t<\/div>
\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\tDatapath<\/h2>\n
Descripci\u00f3n: <\/strong>determina el camino que los datos van a tomar y manda habilita los componentes seg\u00fan las se\u00f1ales del controlador.<\/p>\n\n- RegSrc: determina el tipo de operaci\u00f3n para el regFile<\/li>\n
- RegWrite: habilita escribir en los registros<\/li>\n
- ImmSrc: determina el tipo de operaci\u00f3n para la extensi\u00f3n (proceso de datos, memoria, branches)<\/li>\n
- ALUSrc: coloca inmediato o no<\/li>\n
- ALUControl: tipo de operaci\u00f3n del ALU<\/li>\n
- MemtoReg: si se escribe lo de la memoria en el resultado<\/li>\n
- PCSrc: dice cual ser\u00e1 la siguiente instrucci\u00f3n<\/li>\n
- ReadData: es la salid del data memory<\/li>\n
- PC: Es el n\u00famero de instrucci\u00f3n<\/li>\n
- Instr: la instrucci\u00f3n PC<\/li>\n
- ALUResult, WriteData: resultado del ALU, writeData es lo que se escribir\u00e1 en la memoria<\/li>\n
- ALUFlags: salida de las banderas del ALU<\/li>\n<\/ul>\n
<\/p><\/div>\n\t\t\t<\/div>
\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\tArchivo de registro<\/h2>\n
Descripci\u00f3n:\u00a0<\/strong>El circuito de registro consiste en multiples entradas tales como las entradas de registro de intrsucciones que tienen 4 bits, entradas de registro de 32 bits, un clk para la activaci\u00f3n de dicho componente, el cual se puene inicializar en cero o uno, y dos salidas de registros de 32 bits.<\/p>\n<\/p>\n
Habilitamos la escritura y escribimos un \u201c7\u201d en el Registro 15 como se muestra a continuaci\u00f3n. We3 habilita la escritura, wa3 es el registro destino y wd3 es la data a escribir.<\/p><\/div>\n\t\t\t<\/div>
\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\tExtensi\u00f3n<\/h2>\n
Descripci\u00f3n:\u00a0<\/strong>El circuito de extensi\u00f3n consiste en dos entradas, la instrucci\u00f3n de 24 bits e Inmediato de Origen de 2 bits (00,01,10) y una salida llamada extensi\u00f3n final de 32 bits.<\/p>\n<\/p>\n
Tenemos en el immSrc un \u201c00\u201d que nos indica una operaci\u00f3n de procesamiento de datos. La instrucci\u00f3n del bit 0 al 23 nos indica que el inmediato es un 5. Por lo tanto la extensi\u00f3n nos devuelve un la instrucci\u00f3n del bit 0 al 7 con 24 \u201c0\u201d concatenados.<\/p><\/div>\n\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t<\/div>\n\t\t\t<\/div>\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t<\/div>\n\t\t\t\t\n\t\t\t\t\n\t\t\t<\/div>
\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\tC\u00f3digos<\/h1><\/div>\n\t\t\t<\/div>\n\t\t\t<\/div>\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t<\/div>\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\tARM<\/h5>\n\t\t\t\t\n <\/p>\n
library IEEE;\r\nuse IEEE.STD_LOGIC_1164.ALL;\r\nentity arm is\r\n-- Port ( );\r\n port(clk, reset: in STD_LOGIC;\r\n PC: out STD_LOGIC_VECTOR(31 downto 0);\r\n Instr: in STD_LOGIC_VECTOR(31 downto 0);\r\n MemWrite: out STD_LOGIC;\r\n ALUResult, WriteData: out STD_LOGIC_VECTOR(31 downto 0);\r\n ReadData: in STD_LOGIC_VECTOR(31 downto 0));\r\nend arm;\r\narchitecture struct of arm is\r\n component controller\r\n port(clk, reset: in STD_LOGIC;\r\n Instr: in STD_LOGIC_VECTOR(31 downto 12);\r\n ALUFlags: in STD_LOGIC_VECTOR(3 downto 0);\r\n RegSrc: out STD_LOGIC_VECTOR(1 downto 0);\r\n RegWrite: out STD_LOGIC;\r\n ImmSrc: out STD_LOGIC_VECTOR(1 downto 0);\r\n ALUSrc: out STD_LOGIC;\r\n ALUControl: out STD_LOGIC_VECTOR(1 downto 0);\r\n MemWrite: out STD_LOGIC;\r\n MemtoReg: out STD_LOGIC;\r\n PCSrc: out STD_LOGIC);\r\n end component;\r\n component datap\r\n port(clk, reset: in STD_LOGIC;\r\n RegSrc: in STD_LOGIC_VECTOR(1 downto 0);\r\n RegWrite: in STD_LOGIC;\r\n ImmSrc: in STD_LOGIC_VECTOR(1 downto 0);\r\n ALUSrc: in STD_LOGIC;\r\n ALUControl: in STD_LOGIC_VECTOR(1 downto 0);\r\n MemtoReg: in STD_LOGIC;\r\n PCSrc: in STD_LOGIC;\r\n ALUFlags: out STD_LOGIC_VECTOR(3 downto 0);\r\n PC: buffer STD_LOGIC_VECTOR(31 downto 0);\r\n Instr: in STD_LOGIC_VECTOR(31 downto 0);\r\n ALUResult, WriteData: buffer STD_LOGIC_VECTOR(31 downto 0);\r\n ReadData: in STD_LOGIC_VECTOR(31 downto 0));\r\n end component;\r\nsignal RegWrites, ALUSrcs, MemtoRegs, PCSrcs: STD_LOGIC;\r\nsignal RegSrcs, ImmSrcs, ALUControls: STD_LOGIC_VECTOR (1 downto 0);\r\nsignal ALUFlags: STD_LOGIC_VECTOR(3 downto 0);\r\nsignal PCs, ALUResults, WriteDatas: STD_LOGIC_VECTOR(31 downto 0);\r\nbegin\r\ncont: controller port map(clk, reset, Instr(31 downto 12), ALUFlags, RegSrcs, RegWrites, ImmSrcs, ALUSrcs, ALUControls, MemWrite, MemtoRegs, PCSrcs);\r\ndp: datap port map(clk, reset, RegSrcs, RegWrites, ImmSrcs, ALUSrcs, ALUControls, MemtoRegs, PCSrcs, ALUFlags, PCs, Instr, ALUResults, WriteDatas, ReadData);\r\n--RegWrite<=RegWritesgnl;\r\nALUResult<=ALUResults;\r\n--ReadData<=MemWritesgnl;\r\n--PCSrc<=PCSrcsgnl;\r\nPC<=PCs;\r\nWriteData<=WriteDatas;\r\nend;<\/pre><\/div>\n\t\t\t<\/div>\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\tController<\/h5>\n\t\t\t\t\n <\/p>\n
library IEEE;\r\nuse IEEE.STD_LOGIC_1164.ALL;\r\nentity controller is\r\n-- Port ( );\r\n port(clk, reset: in STD_LOGIC;\r\n Instr: in STD_LOGIC_VECTOR(31 downto 12);\r\n ALUFlags: in STD_LOGIC_VECTOR(3 downto 0);\r\n RegSrc: out STD_LOGIC_VECTOR(1 downto 0);\r\n RegWrite: out STD_LOGIC;\r\n ImmSrc: out STD_LOGIC_VECTOR(1 downto 0);\r\n ALUSrc: out STD_LOGIC;\r\n ALUControl: out STD_LOGIC_VECTOR(1 downto 0);\r\n MemWrite: out STD_LOGIC;\r\n MemtoReg: out STD_LOGIC;\r\n PCSrc: out STD_LOGIC);\r\nend controller;\r\narchitecture struct of controller is\r\n component decoder\r\n port(Op: in STD_LOGIC_VECTOR(1 downto 0);\r\n Funct: in STD_LOGIC_VECTOR(5 downto 0);\r\n Rd: in STD_LOGIC_VECTOR(3 downto 0);\r\n FlagW: out STD_LOGIC_VECTOR(1 downto 0);\r\n PCS, RegW, MemW: out STD_LOGIC;\r\n MemtoReg, ALUSrc: out STD_LOGIC;\r\n ImmSrc, RegSrc: out STD_LOGIC_VECTOR(1 downto 0);\r\n ALUControl: out STD_LOGIC_VECTOR(1 downto 0));\r\n end component;\r\n component conditional\r\n port(clk, reset: in STD_LOGIC;\r\n Cond: in STD_LOGIC_VECTOR(3 downto 0);\r\n ALUFlags: in STD_LOGIC_VECTOR(3 downto 0);\r\n FlagW: in STD_LOGIC_VECTOR(1 downto 0);\r\n PCS, RegW, MemW: in STD_LOGIC;\r\n PCSrc, RegWrite: out STD_LOGIC;\r\n MemWrite: out STD_LOGIC);\r\n end component;\r\nsignal FlagWsgnl: STD_LOGIC_VECTOR(1 downto 0);\r\nsignal PCSsgnl, RegWsgnl, MemWsgnl: STD_LOGIC;\r\nbegin\r\ndec: entity work.decoder port map(Op=>Instr(27 downto 26), Funct=>Instr(25 downto 20), Rd=>Instr(15 downto 12), FlagW=>FlagWsgnl, PCS=>PCSsgnl, RegW=>RegWsgnl, MemW=>MemWsgnl, MemtoReg=>MemtoReg, ALUSrc=>ALUSrc, ImmSrc=>ImmSrc, RegSrc=>RegSrc, ALUControl=>ALUControl);\r\ncl: entity work.conditional port map(clk=>clk, reset=>reset, Cond=>Instr(31 downto 28), ALUFlags=>ALUFlags, FlagW=>FlagWsgnl, PCS=>PCSsgnl, RegW=>RegWsgnl, MemW=>MemWsgnl, PCSrc=>PCSrc, RegWrite=>RegWrite, MemWrite=>MemWrite);\r\nend;<\/pre><\/div>\n\t\t\t<\/div>\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\tDatapath<\/h5>\n\t\t\t\t\n <\/p>\n
library IEEE;\r\nuse IEEE.STD_LOGIC_1164.ALL;\r\nentity datap is\r\n-- Port ( );\r\nport(clk, reset: in STD_LOGIC;\r\nRegSrc: in STD_LOGIC_VECTOR(1 downto 0);\r\nRegWrite: in STD_LOGIC;\r\nImmSrc: in STD_LOGIC_VECTOR(1 downto 0);\r\nALUSrc: in STD_LOGIC;\r\nALUControl: in STD_LOGIC_VECTOR(1 downto 0);\r\nMemtoReg: in STD_LOGIC;\r\nPCSrc: in STD_LOGIC;\r\nALUFlags: out STD_LOGIC_VECTOR(3 downto 0);\r\nPC: buffer STD_LOGIC_VECTOR(31 downto 0);\r\nInstr: in STD_LOGIC_VECTOR(31 downto 0);\r\nALUResult, WriteData: buffer STD_LOGIC_VECTOR(31 downto 0);\r\nReadData: in STD_LOGIC_VECTOR(31 downto 0));\r\nend datap;\r\narchitecture struct of datap is\r\ncomponent alu\r\ngeneric(M: integer :=32);\r\nPort (a,b : in STD_LOGIC_VECTOR (M-1 downto 0);\r\ncontrol : in STD_LOGIC_VECTOR (1 downto 0);\r\nresult : out STD_LOGIC_VECTOR (M-1 downto 0);\r\nflags : out STD_LOGIC_VECTOR (3 downto 0));\r\nend component;\r\ncomponent regfile\r\nport(clk: in STD_LOGIC;\r\nwe3: in STD_LOGIC;\r\nra1, ra2, wa3: in STD_LOGIC_VECTOR(3 downto 0);\r\nwd3, r15: in STD_LOGIC_VECTOR(31 downto 0);\r\nrd1, rd2: out STD_LOGIC_VECTOR(31 downto 0));\r\nend component;\r\ncomponent adder is\r\ngeneric(N: integer := 32);\r\nport(a, b: in STD_LOGIC_VECTOR(N-1 downto 0);\r\ns: out STD_LOGIC_VECTOR(N-1 downto 0);\r\ncin: in STD_LOGIC;\r\ncout: out STD_LOGIC);\r\nend component;\r\ncomponent immediate\r\nport(Instr: in STD_LOGIC_VECTOR(23 downto 0);\r\nImmSrc: in STD_LOGIC_VECTOR(1 downto 0);\r\nExtImm: out STD_LOGIC_VECTOR(31 downto 0));\r\nend component;\r\ncomponent flopenr generic(width: integer:= 4);\r\nport(clk, reset, en: in STD_LOGIC;\r\nd: in STD_LOGIC_VECTOR(width-1 downto 0);\r\nq: out STD_LOGIC_VECTOR(width-1 downto 0));\r\nend component;\r\ncomponent mux21 generic (N: integer:= 4);\r\nPort (c1, c2 : in STD_LOGIC_VECTOR (N-1 downto 0);\r\ns : in STD_LOGIC;\r\nz : out STD_LOGIC_VECTOR (N-1 downto 0));\r\nend component;\r\nsignal PCNext, PCPlus4, PCPlus8: STD_LOGIC_VECTOR(31 downto 0);\r\nsignal ExtImm, Result: STD_LOGIC_VECTOR(31 downto 0);\r\nsignal SrcA, SrcB: STD_LOGIC_VECTOR(31 downto 0);\r\nsignal RA1, RA2: STD_LOGIC_VECTOR(3 downto 0);\r\nsignal PCs: STD_LOGIC_VECTOR(31 downto 0);\r\nsignal writedatas: STD_LOGIC_VECTOR(31 downto 0);\r\nsignal aluresults: STD_LOGIC_VECTOR(31 downto 0);\r\nbegin\r\n-- next PC logic\r\npcmux: mux21 generic map(32) port map(PCPlus4, Result, PCSrc, PCNext);\r\npcreg: flopenr generic map(32) port map(clk, reset, '1', PCNext, pcs);\r\nPC<=pcs;\r\npcadd1: adder port map(PCs, X\"00000004\", PCPlus4,'0');\r\npcadd2: adder port map(PCPlus4, X\"00000004\", PCPlus8,'0');\r\n-- register file logic\r\nra1mux: mux21 generic map (4) port map(Instr(19 downto 16), \"1111\", RegSrc(0), RA1);\r\nra2mux: mux21 generic map (4) port map(Instr(3 downto 0), Instr(15 downto 12), RegSrc(1), RA2);\r\nrf: regfile port map(clk, RegWrite, RA1, RA2, Instr(15 downto 12), Result, PCPlus8, SrcA, writedatas);\r\nWriteData<=writedatas;\r\nresmux: mux21 generic map(32) port map(ALUResults, ReadData, MemtoReg, Result);\r\next: immediate port map(Instr(23 downto 0), ImmSrc, ExtImm);\r\n-- ALU logic\r\nsrcbmux: mux21 generic map(32) port map(writedatas, ExtImm, ALUSrc, SrcB);\r\ni_alu: alu port map(SrcA, SrcB, ALUControl, ALUResults, ALUFlags);\r\nALUResult<=ALUResults;\r\nend;<\/pre>\n <\/p>\n
<\/p><\/div>\n\t\t\t<\/div>\n\t\t\t<\/div>
\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\tRegfile<\/h5>\n\t\t\t\t\n <\/p>\n
library IEEE;\r\nuse IEEE.STD_LOGIC_1164.ALL;\r\nuse IEEE.STD_LOGIC_UNSIGNED.ALL;\r\nuse IEEE.NUMERIC_STD.ALL;\r\n\r\nentity regfile is -- three-port register file\r\n port(clk: in STD_LOGIC;\r\n we3: in STD_LOGIC;\r\n ra1, ra2, wa3: in STD_LOGIC_VECTOR(3 downto 0);\r\n wd3, r15: in STD_LOGIC_VECTOR(31 downto 0);\r\n rd1, rd2: out STD_LOGIC_VECTOR(31 downto 0));\r\nend;\r\n\r\narchitecture behave of regfile is\r\n type ramtype is array (31 downto 0) of\r\n STD_LOGIC_VECTOR(31 downto 0);\r\n signal mem: ramtype;\r\n \r\nbegin\r\n process(clk) begin\r\n if rising_edge(clk) then\r\n if we3 = '1' then \r\n mem(to_integer(unsigned(wa3))) <= wd3;\r\n end if;\r\n end if;\r\n end process;\r\n process(clk, we3, ra1, ra2, wa3, wd3, r15) begin\r\n if (to_integer(unsigned(ra1)) = 15) then \r\n rd1 <= r15;\r\n else \r\n rd1 <= mem(to_integer(unsigned(ra1)));\r\n end if;\r\n if (to_integer(unsigned(ra2)) = 15) then \r\n rd2 <= r15;\r\n else \r\n rd2 <= mem(to_integer(unsigned(ra2)));\r\n end if;\r\n end process;\r\nend;<\/pre>\n <\/p>\n
<\/p><\/div>\n\t\t\t<\/div>
\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\tExtension<\/h5>\n\t\t\t\t\n <\/p>\n
library IEEE; \r\nuse IEEE.STD_LOGIC_1164.all;\r\nentity extend is\r\n port(Instr: in STD_LOGIC_VECTOR(23 downto 0);\r\n ImmSrc: in STD_LOGIC_VECTOR(1 downto 0);\r\n ExtImm: out STD_LOGIC_VECTOR(31 downto 0));\r\nend;\r\narchitecture behave of extend is\r\nbegin\r\n process(Instr, ImmSrc) \r\n begin\r\n case ImmSrc is\r\n when \"00\" => \r\n ExtImm <= (X\"000000\"&Instr(7 downto 0));\r\n when \"01\" => \r\n ExtImm <= (X\"00000\"&Instr(11 downto 0));\r\n when \"10\" => ExtImm <= (Instr(23) & Instr(23) & Instr(23)&Instr(23) & \r\n Instr(23)&Instr(23) & Instr(23 downto 0) & \"00\");\r\n when others => ExtImm <= (others => '-');\r\n end case;\r\n end process;\r\nend;<\/pre>\n <\/p>\n
<\/p><\/div>\n\t\t\t<\/div>\n\t\t\t<\/div>\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t<\/div>\n\t\t\t\t\n\t\t\t\t\n\t\t\t<\/div>
\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\u00a0<\/p>\n
Reflexi\u00f3n<\/h3>\n
El n\u00famero de instrucciones en un programa depende de la arquitectura del procesador. Algunas arquitecturas tienen instrucciones complicadas que hacen m\u00e1s trabajo por instrucci\u00f3n, lo que reduce el n\u00famero de instrucciones en un programa. Sin embargo, estas instrucciones complicadas suelen ser m\u00e1s lentas de ejecutar en hardware.<\/p>\n
La computadora maneja un lenguaje binario. A trav\u00e9s del lenguaje ensamblador, los lenguajes de programaci\u00f3n, diversas interfaces, compiladores y dem\u00e1s podemos facilitar la interacci\u00f3n hombre-m\u00e1quina.<\/p>\n
\u00a0<\/p><\/div>\n\t\t\t<\/div>\n\t\t\t<\/div>\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t<\/div>\n\t\t\t\t\n\t\t\t\t\n\t\t\t<\/div><\/p>\n","protected":false},"excerpt":{"rendered":"","protected":false},"author":18,"featured_media":902,"comment_status":"open","ping_status":"closed","template":"","meta":{"_et_pb_use_builder":"on","_et_pb_old_content":"","_et_gb_content_width":"","footnotes":""},"project_category":[16],"project_tag":[],"class_list":["post-752","project","type-project","status-publish","has-post-thumbnail","hentry","project_category-portafolio-ii"],"_links":{"self":[{"href":"https:\/\/portafoliosfit.um.edu.mx\/sarahhdz\/wp-json\/wp\/v2\/project\/752","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/portafoliosfit.um.edu.mx\/sarahhdz\/wp-json\/wp\/v2\/project"}],"about":[{"href":"https:\/\/portafoliosfit.um.edu.mx\/sarahhdz\/wp-json\/wp\/v2\/types\/project"}],"author":[{"embeddable":true,"href":"https:\/\/portafoliosfit.um.edu.mx\/sarahhdz\/wp-json\/wp\/v2\/users\/18"}],"replies":[{"embeddable":true,"href":"https:\/\/portafoliosfit.um.edu.mx\/sarahhdz\/wp-json\/wp\/v2\/comments?post=752"}],"version-history":[{"count":63,"href":"https:\/\/portafoliosfit.um.edu.mx\/sarahhdz\/wp-json\/wp\/v2\/project\/752\/revisions"}],"predecessor-version":[{"id":1054,"href":"https:\/\/portafoliosfit.um.edu.mx\/sarahhdz\/wp-json\/wp\/v2\/project\/752\/revisions\/1054"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/portafoliosfit.um.edu.mx\/sarahhdz\/wp-json\/wp\/v2\/media\/902"}],"wp:attachment":[{"href":"https:\/\/portafoliosfit.um.edu.mx\/sarahhdz\/wp-json\/wp\/v2\/media?parent=752"}],"wp:term":[{"taxonomy":"project_category","embeddable":true,"href":"https:\/\/portafoliosfit.um.edu.mx\/sarahhdz\/wp-json\/wp\/v2\/project_category?post=752"},{"taxonomy":"project_tag","embeddable":true,"href":"https:\/\/portafoliosfit.um.edu.mx\/sarahhdz\/wp-json\/wp\/v2\/project_tag?post=752"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}
\nDividimos nuestras microarquitecturas en dos partes interactivas: la ruta de datos y la unidad de control. La ruta de datos opera en palabras de datos. Contiene estructuras como memorias, registros, ALU y multiplexores. Estamos implementando la arquitectura ARM de 32 bits, por lo que usamos una ruta de datos de 32 bits.<\/p>\n
La unidad de control recibe la instrucci\u00f3n actual de la ruta de datos y le dice a la ruta de datos c\u00f3mo ejecutar esa instrucci\u00f3n. Espec\u00edficamente, la unidad de control produce se\u00f1ales de selecci\u00f3n de multiplexor, habilitaci\u00f3n de registro y escritura de memoria para controlar el funcionamiento de la ruta de datos.<\/p><\/div>\n\t\t\t<\/div>
<\/span><\/a>\n\t\t\t<\/div>\n\t\t\t<\/div>\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t<\/div>\n\t\t\t\t\n\t\t\t\t\n\t\t\t<\/div>- \n\t\t\t\t\t
- ARM<\/a><\/li>
- Controlador<\/a><\/li>
- Data path<\/a><\/li>
- Reg file<\/a><\/li>
- Extension<\/a><\/li>\n\t\t\t\t<\/ul>\n\t\t\t\t
\n\t\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\tARM - processor<\/h2>\n
Descripci\u00f3n:<\/strong> Nuestra \u00fanica entrada es la instrucci\u00f3n ya que la funci\u00f3n del procesador es procesar instrucciones.<\/p>\n
- \n
- PC:<\/strong> devuelve el n\u00famero de la siguiente instrucci\u00f3n a ejecutar<\/li>\n
- Instr:<\/strong> contiene la instrucci\u00f3n a ejecutar<\/li>\n
- MemWrite:<\/strong> determina si se va a escribir en la memoria<\/li>\n
- ALUResult:<\/strong> WriteData: devuelve el resultado del ALU y el Data a escribir en la memoria<\/li>\n
- ReadData:<\/strong> es una entrada que muestra un dato de la memoria si la instrucci\u00f3n lo requiere<\/li>\n<\/ul>\n
<\/p><\/div>\n\t\t\t<\/div>\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\tControlador<\/h2>\n
Descripci\u00f3n:<\/strong> El controlador es el que controla precisamente al datapath. Decodifica la instrucci\u00f3n para habilitar los componentes del datapath y utiliza un conditional check para verificar las condiciones de la instrucci\u00f3n, as\u00ed como la lectura y escritura de datos en la memoria.<\/p>\n
- \n
- Instr: contiene la instrucci\u00f3n a decodificar<\/li>\n
- ALUFlags: contiene las flags que devuelve el ALU<\/li>\n
- RegSrc: Devuelve el registro origen<\/li>\n
- RegWrite: habilita la escritura en los registros del regFile<\/li>\n
- ImmSrc: Determina el tipo de operaci\u00f3n (procesamiento de datos, memoria o branches)<\/li>\n
- ALUSrc: Habilita la entrada de datos al ALU<\/li>\n
- ALUControl: Determina el tipo de operaci\u00f3n a realizar del ALU<\/li>\n
- MemWrite: Habilita la escritura en la memoria<\/li>\n
- MemtoReg: Permite escribir en un registro lo que hay en la memoria<\/li>\n
- PCSrc: Devuelve el PC del conditionalcheck<\/li>\n<\/ul>\n<\/p><\/div>\n\t\t\t<\/div>\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t
Datapath<\/h2>\n
Descripci\u00f3n: <\/strong>determina el camino que los datos van a tomar y manda habilita los componentes seg\u00fan las se\u00f1ales del controlador.<\/p>\n
- \n
- RegSrc: determina el tipo de operaci\u00f3n para el regFile<\/li>\n
- RegWrite: habilita escribir en los registros<\/li>\n
- ImmSrc: determina el tipo de operaci\u00f3n para la extensi\u00f3n (proceso de datos, memoria, branches)<\/li>\n
- ALUSrc: coloca inmediato o no<\/li>\n
- ALUControl: tipo de operaci\u00f3n del ALU<\/li>\n
- MemtoReg: si se escribe lo de la memoria en el resultado<\/li>\n
- PCSrc: dice cual ser\u00e1 la siguiente instrucci\u00f3n<\/li>\n
- ReadData: es la salid del data memory<\/li>\n
- PC: Es el n\u00famero de instrucci\u00f3n<\/li>\n
- Instr: la instrucci\u00f3n PC<\/li>\n
- ALUResult, WriteData: resultado del ALU, writeData es lo que se escribir\u00e1 en la memoria<\/li>\n
- ALUFlags: salida de las banderas del ALU<\/li>\n<\/ul>\n<\/p><\/div>\n\t\t\t<\/div>\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t
Archivo de registro<\/h2>\n
Descripci\u00f3n:\u00a0<\/strong>El circuito de registro consiste en multiples entradas tales como las entradas de registro de intrsucciones que tienen 4 bits, entradas de registro de 32 bits, un clk para la activaci\u00f3n de dicho componente, el cual se puene inicializar en cero o uno, y dos salidas de registros de 32 bits.<\/p>\n
<\/p>\nHabilitamos la escritura y escribimos un \u201c7\u201d en el Registro 15 como se muestra a continuaci\u00f3n. We3 habilita la escritura, wa3 es el registro destino y wd3 es la data a escribir.<\/p><\/div>\n\t\t\t<\/div>
\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\tExtensi\u00f3n<\/h2>\n
Descripci\u00f3n:\u00a0<\/strong>El circuito de extensi\u00f3n consiste en dos entradas, la instrucci\u00f3n de 24 bits e Inmediato de Origen de 2 bits (00,01,10) y una salida llamada extensi\u00f3n final de 32 bits.<\/p>\n
<\/p>\nTenemos en el immSrc un \u201c00\u201d que nos indica una operaci\u00f3n de procesamiento de datos. La instrucci\u00f3n del bit 0 al 23 nos indica que el inmediato es un 5. Por lo tanto la extensi\u00f3n nos devuelve un la instrucci\u00f3n del bit 0 al 7 con 24 \u201c0\u201d concatenados.<\/p><\/div>\n\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t<\/div>\n\t\t\t<\/div>\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t<\/div>\n\t\t\t\t\n\t\t\t\t\n\t\t\t<\/div>
\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\tC\u00f3digos<\/h1><\/div>\n\t\t\t<\/div>\n\t\t\t<\/div>\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t<\/div>
\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\tARM<\/h5>\n\t\t\t\t
\n <\/p>\n
library IEEE;\r\nuse IEEE.STD_LOGIC_1164.ALL;\r\nentity arm is\r\n-- Port ( );\r\n port(clk, reset: in STD_LOGIC;\r\n PC: out STD_LOGIC_VECTOR(31 downto 0);\r\n Instr: in STD_LOGIC_VECTOR(31 downto 0);\r\n MemWrite: out STD_LOGIC;\r\n ALUResult, WriteData: out STD_LOGIC_VECTOR(31 downto 0);\r\n ReadData: in STD_LOGIC_VECTOR(31 downto 0));\r\nend arm;\r\narchitecture struct of arm is\r\n component controller\r\n port(clk, reset: in STD_LOGIC;\r\n Instr: in STD_LOGIC_VECTOR(31 downto 12);\r\n ALUFlags: in STD_LOGIC_VECTOR(3 downto 0);\r\n RegSrc: out STD_LOGIC_VECTOR(1 downto 0);\r\n RegWrite: out STD_LOGIC;\r\n ImmSrc: out STD_LOGIC_VECTOR(1 downto 0);\r\n ALUSrc: out STD_LOGIC;\r\n ALUControl: out STD_LOGIC_VECTOR(1 downto 0);\r\n MemWrite: out STD_LOGIC;\r\n MemtoReg: out STD_LOGIC;\r\n PCSrc: out STD_LOGIC);\r\n end component;\r\n component datap\r\n port(clk, reset: in STD_LOGIC;\r\n RegSrc: in STD_LOGIC_VECTOR(1 downto 0);\r\n RegWrite: in STD_LOGIC;\r\n ImmSrc: in STD_LOGIC_VECTOR(1 downto 0);\r\n ALUSrc: in STD_LOGIC;\r\n ALUControl: in STD_LOGIC_VECTOR(1 downto 0);\r\n MemtoReg: in STD_LOGIC;\r\n PCSrc: in STD_LOGIC;\r\n ALUFlags: out STD_LOGIC_VECTOR(3 downto 0);\r\n PC: buffer STD_LOGIC_VECTOR(31 downto 0);\r\n Instr: in STD_LOGIC_VECTOR(31 downto 0);\r\n ALUResult, WriteData: buffer STD_LOGIC_VECTOR(31 downto 0);\r\n ReadData: in STD_LOGIC_VECTOR(31 downto 0));\r\n end component;\r\nsignal RegWrites, ALUSrcs, MemtoRegs, PCSrcs: STD_LOGIC;\r\nsignal RegSrcs, ImmSrcs, ALUControls: STD_LOGIC_VECTOR (1 downto 0);\r\nsignal ALUFlags: STD_LOGIC_VECTOR(3 downto 0);\r\nsignal PCs, ALUResults, WriteDatas: STD_LOGIC_VECTOR(31 downto 0);\r\nbegin\r\ncont: controller port map(clk, reset, Instr(31 downto 12), ALUFlags, RegSrcs, RegWrites, ImmSrcs, ALUSrcs, ALUControls, MemWrite, MemtoRegs, PCSrcs);\r\ndp: datap port map(clk, reset, RegSrcs, RegWrites, ImmSrcs, ALUSrcs, ALUControls, MemtoRegs, PCSrcs, ALUFlags, PCs, Instr, ALUResults, WriteDatas, ReadData);\r\n--RegWrite<=RegWritesgnl;\r\nALUResult<=ALUResults;\r\n--ReadData<=MemWritesgnl;\r\n--PCSrc<=PCSrcsgnl;\r\nPC<=PCs;\r\nWriteData<=WriteDatas;\r\nend;<\/pre><\/div>\n\t\t\t<\/div>
\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\tController<\/h5>\n\t\t\t\t
\n <\/p>\n
library IEEE;\r\nuse IEEE.STD_LOGIC_1164.ALL;\r\nentity controller is\r\n-- Port ( );\r\n port(clk, reset: in STD_LOGIC;\r\n Instr: in STD_LOGIC_VECTOR(31 downto 12);\r\n ALUFlags: in STD_LOGIC_VECTOR(3 downto 0);\r\n RegSrc: out STD_LOGIC_VECTOR(1 downto 0);\r\n RegWrite: out STD_LOGIC;\r\n ImmSrc: out STD_LOGIC_VECTOR(1 downto 0);\r\n ALUSrc: out STD_LOGIC;\r\n ALUControl: out STD_LOGIC_VECTOR(1 downto 0);\r\n MemWrite: out STD_LOGIC;\r\n MemtoReg: out STD_LOGIC;\r\n PCSrc: out STD_LOGIC);\r\nend controller;\r\narchitecture struct of controller is\r\n component decoder\r\n port(Op: in STD_LOGIC_VECTOR(1 downto 0);\r\n Funct: in STD_LOGIC_VECTOR(5 downto 0);\r\n Rd: in STD_LOGIC_VECTOR(3 downto 0);\r\n FlagW: out STD_LOGIC_VECTOR(1 downto 0);\r\n PCS, RegW, MemW: out STD_LOGIC;\r\n MemtoReg, ALUSrc: out STD_LOGIC;\r\n ImmSrc, RegSrc: out STD_LOGIC_VECTOR(1 downto 0);\r\n ALUControl: out STD_LOGIC_VECTOR(1 downto 0));\r\n end component;\r\n component conditional\r\n port(clk, reset: in STD_LOGIC;\r\n Cond: in STD_LOGIC_VECTOR(3 downto 0);\r\n ALUFlags: in STD_LOGIC_VECTOR(3 downto 0);\r\n FlagW: in STD_LOGIC_VECTOR(1 downto 0);\r\n PCS, RegW, MemW: in STD_LOGIC;\r\n PCSrc, RegWrite: out STD_LOGIC;\r\n MemWrite: out STD_LOGIC);\r\n end component;\r\nsignal FlagWsgnl: STD_LOGIC_VECTOR(1 downto 0);\r\nsignal PCSsgnl, RegWsgnl, MemWsgnl: STD_LOGIC;\r\nbegin\r\ndec: entity work.decoder port map(Op=>Instr(27 downto 26), Funct=>Instr(25 downto 20), Rd=>Instr(15 downto 12), FlagW=>FlagWsgnl, PCS=>PCSsgnl, RegW=>RegWsgnl, MemW=>MemWsgnl, MemtoReg=>MemtoReg, ALUSrc=>ALUSrc, ImmSrc=>ImmSrc, RegSrc=>RegSrc, ALUControl=>ALUControl);\r\ncl: entity work.conditional port map(clk=>clk, reset=>reset, Cond=>Instr(31 downto 28), ALUFlags=>ALUFlags, FlagW=>FlagWsgnl, PCS=>PCSsgnl, RegW=>RegWsgnl, MemW=>MemWsgnl, PCSrc=>PCSrc, RegWrite=>RegWrite, MemWrite=>MemWrite);\r\nend;<\/pre><\/div>\n\t\t\t<\/div>
\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\tDatapath<\/h5>\n\t\t\t\t
\n <\/p>\n
library IEEE;\r\nuse IEEE.STD_LOGIC_1164.ALL;\r\nentity datap is\r\n-- Port ( );\r\nport(clk, reset: in STD_LOGIC;\r\nRegSrc: in STD_LOGIC_VECTOR(1 downto 0);\r\nRegWrite: in STD_LOGIC;\r\nImmSrc: in STD_LOGIC_VECTOR(1 downto 0);\r\nALUSrc: in STD_LOGIC;\r\nALUControl: in STD_LOGIC_VECTOR(1 downto 0);\r\nMemtoReg: in STD_LOGIC;\r\nPCSrc: in STD_LOGIC;\r\nALUFlags: out STD_LOGIC_VECTOR(3 downto 0);\r\nPC: buffer STD_LOGIC_VECTOR(31 downto 0);\r\nInstr: in STD_LOGIC_VECTOR(31 downto 0);\r\nALUResult, WriteData: buffer STD_LOGIC_VECTOR(31 downto 0);\r\nReadData: in STD_LOGIC_VECTOR(31 downto 0));\r\nend datap;\r\narchitecture struct of datap is\r\ncomponent alu\r\ngeneric(M: integer :=32);\r\nPort (a,b : in STD_LOGIC_VECTOR (M-1 downto 0);\r\ncontrol : in STD_LOGIC_VECTOR (1 downto 0);\r\nresult : out STD_LOGIC_VECTOR (M-1 downto 0);\r\nflags : out STD_LOGIC_VECTOR (3 downto 0));\r\nend component;\r\ncomponent regfile\r\nport(clk: in STD_LOGIC;\r\nwe3: in STD_LOGIC;\r\nra1, ra2, wa3: in STD_LOGIC_VECTOR(3 downto 0);\r\nwd3, r15: in STD_LOGIC_VECTOR(31 downto 0);\r\nrd1, rd2: out STD_LOGIC_VECTOR(31 downto 0));\r\nend component;\r\ncomponent adder is\r\ngeneric(N: integer := 32);\r\nport(a, b: in STD_LOGIC_VECTOR(N-1 downto 0);\r\ns: out STD_LOGIC_VECTOR(N-1 downto 0);\r\ncin: in STD_LOGIC;\r\ncout: out STD_LOGIC);\r\nend component;\r\ncomponent immediate\r\nport(Instr: in STD_LOGIC_VECTOR(23 downto 0);\r\nImmSrc: in STD_LOGIC_VECTOR(1 downto 0);\r\nExtImm: out STD_LOGIC_VECTOR(31 downto 0));\r\nend component;\r\ncomponent flopenr generic(width: integer:= 4);\r\nport(clk, reset, en: in STD_LOGIC;\r\nd: in STD_LOGIC_VECTOR(width-1 downto 0);\r\nq: out STD_LOGIC_VECTOR(width-1 downto 0));\r\nend component;\r\ncomponent mux21 generic (N: integer:= 4);\r\nPort (c1, c2 : in STD_LOGIC_VECTOR (N-1 downto 0);\r\ns : in STD_LOGIC;\r\nz : out STD_LOGIC_VECTOR (N-1 downto 0));\r\nend component;\r\nsignal PCNext, PCPlus4, PCPlus8: STD_LOGIC_VECTOR(31 downto 0);\r\nsignal ExtImm, Result: STD_LOGIC_VECTOR(31 downto 0);\r\nsignal SrcA, SrcB: STD_LOGIC_VECTOR(31 downto 0);\r\nsignal RA1, RA2: STD_LOGIC_VECTOR(3 downto 0);\r\nsignal PCs: STD_LOGIC_VECTOR(31 downto 0);\r\nsignal writedatas: STD_LOGIC_VECTOR(31 downto 0);\r\nsignal aluresults: STD_LOGIC_VECTOR(31 downto 0);\r\nbegin\r\n-- next PC logic\r\npcmux: mux21 generic map(32) port map(PCPlus4, Result, PCSrc, PCNext);\r\npcreg: flopenr generic map(32) port map(clk, reset, '1', PCNext, pcs);\r\nPC<=pcs;\r\npcadd1: adder port map(PCs, X\"00000004\", PCPlus4,'0');\r\npcadd2: adder port map(PCPlus4, X\"00000004\", PCPlus8,'0');\r\n-- register file logic\r\nra1mux: mux21 generic map (4) port map(Instr(19 downto 16), \"1111\", RegSrc(0), RA1);\r\nra2mux: mux21 generic map (4) port map(Instr(3 downto 0), Instr(15 downto 12), RegSrc(1), RA2);\r\nrf: regfile port map(clk, RegWrite, RA1, RA2, Instr(15 downto 12), Result, PCPlus8, SrcA, writedatas);\r\nWriteData<=writedatas;\r\nresmux: mux21 generic map(32) port map(ALUResults, ReadData, MemtoReg, Result);\r\next: immediate port map(Instr(23 downto 0), ImmSrc, ExtImm);\r\n-- ALU logic\r\nsrcbmux: mux21 generic map(32) port map(writedatas, ExtImm, ALUSrc, SrcB);\r\ni_alu: alu port map(SrcA, SrcB, ALUControl, ALUResults, ALUFlags);\r\nALUResult<=ALUResults;\r\nend;<\/pre>\n
<\/p>\n
<\/p><\/div>\n\t\t\t<\/div>\n\t\t\t<\/div>
\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\tRegfile<\/h5>\n\t\t\t\t
\n <\/p>\n
library IEEE;\r\nuse IEEE.STD_LOGIC_1164.ALL;\r\nuse IEEE.STD_LOGIC_UNSIGNED.ALL;\r\nuse IEEE.NUMERIC_STD.ALL;\r\n\r\nentity regfile is -- three-port register file\r\n port(clk: in STD_LOGIC;\r\n we3: in STD_LOGIC;\r\n ra1, ra2, wa3: in STD_LOGIC_VECTOR(3 downto 0);\r\n wd3, r15: in STD_LOGIC_VECTOR(31 downto 0);\r\n rd1, rd2: out STD_LOGIC_VECTOR(31 downto 0));\r\nend;\r\n\r\narchitecture behave of regfile is\r\n type ramtype is array (31 downto 0) of\r\n STD_LOGIC_VECTOR(31 downto 0);\r\n signal mem: ramtype;\r\n \r\nbegin\r\n process(clk) begin\r\n if rising_edge(clk) then\r\n if we3 = '1' then \r\n mem(to_integer(unsigned(wa3))) <= wd3;\r\n end if;\r\n end if;\r\n end process;\r\n process(clk, we3, ra1, ra2, wa3, wd3, r15) begin\r\n if (to_integer(unsigned(ra1)) = 15) then \r\n rd1 <= r15;\r\n else \r\n rd1 <= mem(to_integer(unsigned(ra1)));\r\n end if;\r\n if (to_integer(unsigned(ra2)) = 15) then \r\n rd2 <= r15;\r\n else \r\n rd2 <= mem(to_integer(unsigned(ra2)));\r\n end if;\r\n end process;\r\nend;<\/pre>\n
<\/p>\n
<\/p><\/div>\n\t\t\t<\/div>
\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\tExtension<\/h5>\n\t\t\t\t
\n <\/p>\n
library IEEE; \r\nuse IEEE.STD_LOGIC_1164.all;\r\nentity extend is\r\n port(Instr: in STD_LOGIC_VECTOR(23 downto 0);\r\n ImmSrc: in STD_LOGIC_VECTOR(1 downto 0);\r\n ExtImm: out STD_LOGIC_VECTOR(31 downto 0));\r\nend;\r\narchitecture behave of extend is\r\nbegin\r\n process(Instr, ImmSrc) \r\n begin\r\n case ImmSrc is\r\n when \"00\" => \r\n ExtImm <= (X\"000000\"&Instr(7 downto 0));\r\n when \"01\" => \r\n ExtImm <= (X\"00000\"&Instr(11 downto 0));\r\n when \"10\" => ExtImm <= (Instr(23) & Instr(23) & Instr(23)&Instr(23) & \r\n Instr(23)&Instr(23) & Instr(23 downto 0) & \"00\");\r\n when others => ExtImm <= (others => '-');\r\n end case;\r\n end process;\r\nend;<\/pre>\n
<\/p>\n
<\/p><\/div>\n\t\t\t<\/div>\n\t\t\t<\/div>\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t<\/div>\n\t\t\t\t\n\t\t\t\t\n\t\t\t<\/div>
\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\u00a0<\/p>\n
Reflexi\u00f3n<\/h3>\n
El n\u00famero de instrucciones en un programa depende de la arquitectura del procesador. Algunas arquitecturas tienen instrucciones complicadas que hacen m\u00e1s trabajo por instrucci\u00f3n, lo que reduce el n\u00famero de instrucciones en un programa. Sin embargo, estas instrucciones complicadas suelen ser m\u00e1s lentas de ejecutar en hardware.<\/p>\n
La computadora maneja un lenguaje binario. A trav\u00e9s del lenguaje ensamblador, los lenguajes de programaci\u00f3n, diversas interfaces, compiladores y dem\u00e1s podemos facilitar la interacci\u00f3n hombre-m\u00e1quina.<\/p>\n
\u00a0<\/p><\/div>\n\t\t\t<\/div>\n\t\t\t<\/div>\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t\t\n\t\t\t<\/div>\n\t\t\t\t\n\t\t\t\t\n\t\t\t<\/div><\/p>\n","protected":false},"excerpt":{"rendered":"","protected":false},"author":18,"featured_media":902,"comment_status":"open","ping_status":"closed","template":"","meta":{"_et_pb_use_builder":"on","_et_pb_old_content":"","_et_gb_content_width":"","footnotes":""},"project_category":[16],"project_tag":[],"class_list":["post-752","project","type-project","status-publish","has-post-thumbnail","hentry","project_category-portafolio-ii"],"_links":{"self":[{"href":"https:\/\/portafoliosfit.um.edu.mx\/sarahhdz\/wp-json\/wp\/v2\/project\/752","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/portafoliosfit.um.edu.mx\/sarahhdz\/wp-json\/wp\/v2\/project"}],"about":[{"href":"https:\/\/portafoliosfit.um.edu.mx\/sarahhdz\/wp-json\/wp\/v2\/types\/project"}],"author":[{"embeddable":true,"href":"https:\/\/portafoliosfit.um.edu.mx\/sarahhdz\/wp-json\/wp\/v2\/users\/18"}],"replies":[{"embeddable":true,"href":"https:\/\/portafoliosfit.um.edu.mx\/sarahhdz\/wp-json\/wp\/v2\/comments?post=752"}],"version-history":[{"count":63,"href":"https:\/\/portafoliosfit.um.edu.mx\/sarahhdz\/wp-json\/wp\/v2\/project\/752\/revisions"}],"predecessor-version":[{"id":1054,"href":"https:\/\/portafoliosfit.um.edu.mx\/sarahhdz\/wp-json\/wp\/v2\/project\/752\/revisions\/1054"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/portafoliosfit.um.edu.mx\/sarahhdz\/wp-json\/wp\/v2\/media\/902"}],"wp:attachment":[{"href":"https:\/\/portafoliosfit.um.edu.mx\/sarahhdz\/wp-json\/wp\/v2\/media?parent=752"}],"wp:term":[{"taxonomy":"project_category","embeddable":true,"href":"https:\/\/portafoliosfit.um.edu.mx\/sarahhdz\/wp-json\/wp\/v2\/project_category?post=752"},{"taxonomy":"project_tag","embeddable":true,"href":"https:\/\/portafoliosfit.um.edu.mx\/sarahhdz\/wp-json\/wp\/v2\/project_tag?post=752"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}
- Instr:<\/strong> contiene la instrucci\u00f3n a ejecutar<\/li>\n
- Controlador<\/a><\/li>